Memory controllers field and execute memory access requests, for example requests to read data from, and write data to, a plurality of memory modules. A memory access request may be initiated by either a central processing unit (CPU) or an input/output (I/O) device.
A conventional memory controller system can be directly coupled with a plurality of memory modules for access thereto in a direct attach mode. In such a configuration, memory modules may be added in pairs and, accordingly, memory replacement costs are minimized. However, system bandwidth and latency issues are not optimized in a conventional direct attach procedure because as many as eight data transfers must be performed on the memory modules in order for the memory controller system to execute a cache line transaction.
An enhanced memory controller system attach is provided by a conventional mux-mode attach configuration in which the memory controller system attaches to an intermediate chip that is coupled with a plurality of memory modules. In such a configuration, a double-speed bus interconnects the intermediate chip with the memory controller system and dual single-speed memory buses interconnect a plurality of memory modules with the intermediate chip. Accordingly, double width data transfers are made between the intermediate chip and the memory modules and the intermediate chip may merge the data onto the double-speed bus so that the memory controller system may execute a cache line transaction by executing ½ the number of data bursts required in a direct attach system. System latency and bandwidth are thus optimized.